EPCQ256SI16N Datasheet, PDF (39/42 Pages) Altera Corporation – Quad-Serial Configuration (EPCQ) Devices Datasheet

Pin Information
Page 39
Table 27. EPCQ Device Pin Description—Preliminary (Part 2 of 3)
AS x1 Pin-Out Diagram
AS x4 Pin-Out Diagram
Pin Name
DATA2
DATA3
nCS
Pin Number
in 8-Pin
SOIC
Package
—
—
1
Pin Number
in 16-Pin
SOIC
Package
—
—
7
Pin Number
in 8-Pin
SOIC
Package
3
7
1
Pin Number
in 16-Pin
SOIC
Package
9
1
7
Pin Type
I/O
I/O
Input
Description
For AS x1 mode, extended dual input fast write
bytes operation and extended dual input fast read
operation, this pin must connect to a 3.3-V power
supply.
For AS x4 mode, use this pin as an output signal
that serially transfers data out of the EPCQ device
to the FPGA during read or configuration
operations. The transition of the signal is on the
falling edge of the DCLK signal.
During the extended quad input fast write bytes
operation, this pin acts as an input pin that serially
transfers data into the EPCQ device. The data is
latched on the rising edge of the DCLK signal.
During the extended quad input fast read
operation, this pin acts as an output signal pin that
serially transfers data out of the EPCQ device to
the FPGA. The data is shifted out on the falling
edge of the DCLK signal.
For AS x1 mode, extended dual input fast write
bytes operation and extended dual input fast read
operation, this pin must connect to a 3.3-V power
supply.
For AS x4 mode, use this pin as an output signal
that serially transfers data out of the EPCQ device
to the FPGA during read or configuration
operations. The transition of the signal is on the
falling edge of the DCLK signal.
During the extended quad input fast write bytes
operation, this pin acts as an input pin that serially
transfers data into the EPCQ device. The data is
latched on the rising edge of the DCLK signal.
During the extended quad input fast read
operation, this pin acts as an output signal pin that
serially transfers data out of the EPCQ device to
the FPGA. The data is shifted out on the falling
edge of the DCLK signal.
The active low nCS input signal toggles at the
beginning and end of a valid operation. When this
signal is high, the device is deselected and the
DATA pin is tri-stated. When this signal is low, the
device is enabled and is in active mode. After
power up, the EPCQ device requires a falling edge
on the nCS signal before you begin any operation.
July 2012 Altera Corporation
Quad-Serial Configuration (EPCQ) Devices Datasheet