EPM3512AQC208-10N Datasheet, PDF (37/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 3000A Programmable Logic Device Family Data Sheet
Table 24. EPM3512A External Timing Parameters Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7
-10
Min Max Min Max
t_AH
t_ACO1
t_ACH
t_ACL
t_CPPW
t_CNT
f_CNT
t_ACNT
f_ACNT
Array clock hold time
(2)
0.2
Array clock to output delay
C1 = 35 pF (2) 1.0
7.8
Array clock high time
3.0
Array clock low time
3.0
Minimum pulse width for clear (3)
3.0
and preset
Minimum global clock period (2)
8.6
Maximum internal global clock (2), (4)
116.3
frequency
Minimum array clock period (2)
8.6
Maximum internal array clock (2), (4)
frequency
116.3
0.3
1.0
10.4
4.0
4.0
4.0
11.5
87.0
11.5
87.0
Unit
ns
ns
ns
ns
ns
ns
MHz
ns
MHz
Table 25. EPM3512A Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
Min Max Min Max
t_IN
t_IO
t_FIN
t_SEXP
t_PEXP
t_LAD
t_LAC
t_IOE
t_OD1
t_OD2
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay,
slow slew rate = off
V_CCIO = 3.3 V
Output buffer and pad delay,
slow slew rate = off
V_CCIO = 2.5 V
C1 = 35 pF
C1 = 35 pF
0.7
0.9
ns
0.7
0.9
ns
3.1
3.6
ns
2.7
3.5
ns
0.4
0.5
ns
2.2
2.8
ns
1.0
1.3
ns
0.0
0.0
ns
1.0
1.5
ns
1.5
2.0
ns
Altera Corporation
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