D83C Datasheet, PDF (37/106 Pages) Bi technologies – Single-In-Line

Global Clock Network and Phase-Locked Loops
Dual-Purpose Clock Pins
Each Cyclone device except the EP1C3 device has eight dual-purpose
clock pins, DPCLK[7..0] (two on each I/O bank). EP1C3 devices have
five DPCLK pins in the 100-pin TQFP package. These dual-purpose pins
can connect to the global clock network (see Figure 2–22) for high-fanout
control signals such as clocks, asynchronous clears, presets, and clock
enables, or protocol control signals such as TRDY and IRDY for PCI, or
DQS signals for external memory interfaces.
Combined Resources
Each Cyclone device contains eight distinct dedicated clocking resources.
The device uses multiplexers with these clocks to form six-bit buses to
drive LAB row clocks, column IOE clocks, or row IOE clocks. See
Figure 2–23. Another multiplexer at the LAB level selects two of the six
LAB row clocks to feed the LE registers within the LAB.
Figure 2–23. Global Clock Network Multiplexers
Global Clocks [3..0]
Dual-Purpose Clocks [7..0]
PLL Outputs [3..0]
Core Logic [7..0]
Global Clock
Network
Clock [7..0]
Column I/O Region
IO_CLK]5..0]
LAB Row Clock [5..0]
Row I/O Region
IO_CLK[5..0]
IOE clocks have row and column block regions. Six of the eight global
clock resources feed to these row and column regions. Figure 2–24 shows
the I/O clock regions.
Altera Corporation
May 2008
2–31
Preliminary