EPM3256ATC144-7 Datasheet, PDF (34/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 3000A Programmable Logic Device Family Data Sheet
Table 21. EPM3128A Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol
Parameter
t_SU
t_H
t_RD
t_COMB
t_IC
t_EN
t_GLOB
t_PRE
t_CLR
t_PIA
t_LPA
Register setup time
Register hold time
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low–power adder
Conditions
(2)
(5)
Speed Grade
Unit
–5
–7
–10
Min Max Min Max Min Max
1.4
2.1
2.9
ns
0.6
1.0
1.3
ns
0.8
1.2
1.6 ns
0.5
0.9
1.3 ns
1.2
1.7
2.2 ns
0.7
1.0
1.3 ns
1.1
1.6
2.0 ns
1.4
2.0
2.7 ns
1.4
2.0
2.7 ns
1.4
2.0
2.6 ns
4.0
4.0
5.0 ns
Table 22. EPM3256A External Timing Parameters Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–7
–10
Min
Max
Min
Max
t_PD1
t_PD2
t_SU
t_H
t_CO1
t_CH
t_CL
t_ASU
t_AH
t_ACO1
t_ACH
t_ACL
t_CPPW
Input to non–registered
output
C1 = 35 pF (2)
I/O input to non–registered C1 = 35 pF (2)
output
Global clock setup time (2)
5.2
Global clock hold time
(2)
0.0
Global clock to output
C1 = 35 pF
1.0
delay
Global clock high time
3.0
Global clock low time
3.0
Array clock setup time
(2)
2.7
Array clock hold time
(2)
0.3
Array clock to output delay C1 = 35 pF (2) 1.0
Array clock high time
3.0
Array clock low time
3.0
Minimum pulse width for (3)
3.0
clear and preset
7.5
10
ns
7.5
10
ns
6.9
ns
0.0
ns
4.8
1.0
6.4
ns
4.0
ns
4.0
ns
3.6
ns
0.5
ns
7.3
1.0
9.7
ns
4.0
ns
4.0
ns
4.0
ns
34
Altera Corporation