EPM7032LC44-15 Datasheet, PDF (33/66 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000 Programmable Logic Device Family Data Sheet
Table 21. MAX 7000 & MAX 7000E External Timing Parameters Note (1)
Symbol
Parameter
Conditions
t_PD1
t_PD2
t_SU
t_H
t_FSU
t_FH
t_CO1
t_CH
t_CL
t_ASU
t_AH
t_ACO1
t_ACH
t_ACL
t_CPPW
t_ODH
t_CNT
f_CNT
t_ACNT
f_ACNT
f_MAX
Input to non-registered output
C1 = 35 pF
I/O input to non-registered output C1 = 35 pF
Global clock setup time
Global clock hold time
Global clock setup time of fast input (2)
Global clock hold time of fast input (2)
Global clock to output delay
C1 = 35 pF
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
C1 = 35 pF
Array clock high time
Array clock low time
Minimum pulse width for clear and (3)
preset
Output data hold time after clock C1 = 35 pF (4)
Minimum global clock period
Maximum internal global clock
(5)
frequency
Minimum array clock period
Maximum internal array clock
(5)
frequency
Maximum clock frequency
(6)
Speed Grade
Unit
MAX 7000E (-10P) MAX 7000 (-10)
MAX 7000E (-10)
Min Max Min Max
10.0
10.0 ns
10.0
10.0 ns
7.0
8.0
ns
0.0
0.0
ns
3.0
3.0
ns
0.5
0.5
ns
5.0
5
ns
4.0
4.0
ns
4.0
4.0
ns
2.0
3.0
ns
3.0
3.0
ns
10.0
10.0 ns
4.0
4.0
ns
4.0
4.0
ns
4.0
4.0
ns
1.0
100.0
1.0
ns
10.0
10.0 ns
100.0
MHz
100.0
10.0
10.0 ns
100.0
MHz
125.0
125.0
MHz
Altera Corporation
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