MAX3000A Datasheet, PDF (32/42 Pages) Altera Corporation – Programmable Logic Device Family

MAX 3000A Programmable Logic Device Family Data Sheet
Table 21. EPM3512A External Timing Parameters Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7
-10
t_PD1
t_PD2
t_SU
t_H
t_FSU
t_FH
t_CO1
t_CH
t_CL
t_ASU
t_AH
t_ACO1
t_ACH
t_ACL
t_CPPW
t_CNT
f_CNT
t_ACNT
f_ACNT
Min Max
Input to non-registered output C1 = 35 pF (2)
7.5
I/O input to non-registered
C1 = 35 pF (2)
7.5
output
Global clock setup time
(2)
5.6
Global clock hold time
(2)
0.0
Global clock setup time of fast
3.0
input
Global clock hold time of fast
0.0
input
Global clock to output delay C1 = 35 pF
1.0
4.7
Global clock high time
3.0
Global clock low time
3.0
Array clock setup time
(2)
2.5
Array clock hold time
(2)
0.2
Array clock to output delay
C1 = 35 pF (2) 1.0
7.8
Array clock high time
3.0
Array clock low time
3.0
Minimum pulse width for clear (3)
3.0
and preset
Minimum global clock period (2)
8.6
Maximum internal global clock (2), (4)
frequency
116.3
Minimum array clock period (2)
8.6
Maximum internal array clock (2), (4)
frequency
116.3
Min
7.6
0.0
3.0
0.0
1.0
4.0
4.0
3.5
0.3
1.0
4.0
4.0
4.0
87.0
87.0
Max
10.0
10.0
6.3
10.4
11.5
11.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
MHz
Table 22. EPM3512A Internal Timing Parameters (Part 1 of 3) Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
Min Max Min Max
t_IN
Input pad and buffer delay
t_IO
I/O input pad and buffer delay
t_FIN
Fast input delay
0.7
0.9
ns
0.7
0.9
ns
3.1
3.6
ns
32
Altera Corporation