EPM7032AETC44-10N Datasheet, PDF (32/64 Pages) Altera Corporation – Programmable Logic Device

MAX 7000A Programmable Logic Device Data Sheet
Figure 11. MAX 7000A Timing Model
Input
Delay
t_IN
PIA
Delay
t _PIA
Internal Output
Enable Delay
t _IOE
Global Control
Delay
t _GLOB
Logic Array
Delay
t _LAD
Register
Control Delay
t _LAC
t_IC
t _EN
Shared
Expander Delay
t _SEXP
Parallel
Expander Delay
t _PEXP
Register
Delay
t _SU
t_H
t _PRE
t _CLR
t _RD
t _COMB
t _FSU
t _FH
Fast
Input Delay
t_FIN
Output
Delay
t _OD1
t _OD2
t _OD3
t _XZ
t _{Z X1}
t _{Z X2}
t _{Z X3}
I/O
Delay
t_IO
f
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters. Figure 12 shows the timing relationship
between internal and external delay parameters.
See Application Note 94 (Understanding MAX 7000 Timing) for more
information.
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Altera Corporation