EPM7128STC100-15 Datasheet, PDF (30/66 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000 Programmable Logic Device Family Data Sheet
Figure 13. Switching Waveforms
t_R & t_F < 3 ns.
Inputs are driven at 3 V
for a logic high and 0 V
for a logic low. All timing
characteristics are
measured at 1.5 V.
Input Pin
I/O Pin
Combinatorial Mode
t_IN
t_IO
t_PIA
PIA Delay
Shared Expander
Delay
Logic Array
Input
Parallel Expander
Delay
Logic Array
Output
Output Pin
t_SEXP
t_LAC , t_LAD
t_PEXP
t_COMB
t_OD
Global Clock Mode
Global
t_R
t_CH
t_CL
t_F
Clock Pin
Global Clock
t_IN
t_GLOB
at Register
t_SU t_H
Data or Enable
(Logic Array Output)
Array Clock Mode
t_R
t_ACH
t_ACL
Input or I/O Pin
t_IN
t_IO
Clock into PIA
Clock into
t_PIA
Logic Array
Clock at
Register
Data from
Logic Array
Register to PIA
to Logic Array
Register Output
to Pin
t_IC
t_SU
t_H
t_RD
t_PIA
t_OD
t_F
t_CLR , t_PRE
t_PIA
t_OD
30
Altera Corporation