EPC1441TC32N Datasheet, PDF (30/36 Pages) Altera Corporation – Enhanced Configuration (EPC) Devices Datasheet

Page 30
Timing Information
Table 14. EPC Device Configuration Parameters (Part 2 of 2)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
t_ECLK
t_ECLKH
t_ECLKL
t_ECLKR
t_ECLKF
t_POR ⁽⁴⁾
EXCLK input period
EXCLK input duty cycle high time
EXCLK input duty cycle low time
EXCLK input rise time
EXCLK input fall time
POR time
—
10
40% duty cycle
4
40% duty cycle
4
100 MHz
—
100 MHz
—
2 ms
1
100 ms
70
—
—
ns
—
—
ns
—
—
ns
—
3
ns
—
3
ns
2
3
ms
100
120
ms
Notes to Table 14:
(1) To calculate t_OH, use the following equation: t_OH = 0.5 (DCLK period) - 2.5 ns.
(2) This parameter is used for CRC error detection by the FPGA.
(3) This parameter is used for CONF_DONE error detection by the EPC device.
(4) The FPGA V_CCINT ramp time should be less than 1 ms for 2-ms POR and it should be less than 70 ms for 100-ms POR.
Enhanced Configuration (EPC) Devices Datasheet
January 2012 Altera Corporation