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EP4CE10F17C8N Datasheet, PDF (30/42 Pages) Altera Corporation – Cyclone IV Device Datasheet | |||
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1â30
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1â32. Emulated RSDS_E_1R Transmitter Timing Specifications for Cyclone IV Devices (1), (3) (Part 2 of 2)
Symbol
Modes
C6
C7, I7
C8, A7
C8L, I8L
C9L
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
tLOCK (2)
â
â â 1 â â 1 â â 1 â â 1 â â 1 ms
Notes to Table 1â32:
(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O Banks of Cyclone IV E devices and I/O Banks 3, 4, 5, 6, 7, 8, and 9 of Cyclone IV GX
devices.
(2) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and
A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1â33. Mini-LVDS Transmitter Timing Specifications for Cyclone IV Devices (1), (2), (4)
Symbol
Modes
C6
C7, I7
C8, A7
C8L, I8L
C9L
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Ã10
5 â 200 5 â 155.5 5 â 155.5 5 â 155.5 5 â 132.5 MHz
Ã8
5 â 200 5 â 155.5 5 â 155.5 5 â 155.5 5 â 132.5 MHz
fHSCLK (input
Ã7
5 â 200 5 â 155.5 5 â 155.5 5 â 155.5 5 â 132.5 MHz
clock
frequency)
Ã4
5 â 200 5 â 155.5 5 â 155.5 5 â 155.5 5 â 132.5 MHz
Ã2
5 â 200 5 â 155.5 5 â 155.5 5 â 155.5 5 â 132.5 MHz
Ã1
5 â 400 5 â 311 5 â 311 5 â 311 5 â 265 MHz
Ã10 100 â 400 100 â 311 100 â 311 100 â 311 100 â 265 Mbps
Device
operation in
Mbps
Ã8
80 â 400 80 â 311 80 â 311 80 â 311 80 â 265 Mbps
Ã7
70 â 400 70 â 311 70 â 311 70 â 311 70 â 265 Mbps
Ã4
40 â 400 40 â 311 40 â 311 40 â 311 40 â 265 Mbps
Ã2
20 â 400 20 â 311 20 â 311 20 â 311 20 â 265 Mbps
Ã1
10 â 400 10 â 311 10 â 311 10 â 311 10 â 265 Mbps
tDUTY
TCCS
â
45 â 55 45 â 55 45 â 55 45 â 55 45 â 55 %
â
â â 200 â â 200 â â 200 â â 200 â â 200 ps
Output jitter
(peak to peak)
â
â â 500 â â 500 â â 550 â â 600 â â 700 ps
20 â 80%,
tRISE
CLOAD =
â 500 â â 500 â â 500 â â 500 â â 500 â ps
5 pF
20 â 80%,
tFALL
CLOAD =
â 500 â â 500 â â 500 â â 500 â â 500 â ps
5 pF
tLOCK (3)
â
â â 1 â â 1 â â 1 â â 1 â â 1 ms
Notes to Table 1â33:
(1) Applicable for true and emulated mini-LVDS transmitter.
(2) Cyclone IV Eâtrue mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated mini-LVDS transmitter is supported at
the output pin of all I/O banks.
Cyclone IV GXâtrue mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated mini-LVDS transmitter is supported at the
output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(3) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and
A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Cyclone IV Device Handbook,
Volume 3
October 2012 Altera Corporation
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