5M570ZT144I5N Datasheet, PDF (30/30 Pages) Altera Corporation – 3. DC and Switching Characteristics for MAX V Devices

3–30
Chapter 3: DC and Switching Characteristics for MAX V Devices
Document Revision History
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
t_JSXZ
Update register valid output to high impedance
—
25
ns
Notes to Table 3–41:
(1) Minimum clock period specified for 10 pF load on the TDO pin. Larger loads on TDO degrades the maximum TCK frequency.
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and
1.5-V LVCMOS operation, the t_JPSU minimum is 6 ns and t_JPCO, t_JPZX, and t_JPXZ are maximum values at 35 ns.
Document Revision History
Table 3–42 lists the revision history for this chapter.
Table 3–42. Document Revision History
Date
May 2011
January 2011
December 2010
Version
1.2
1.1
1.0
Changes
Updated Table 3–2, Table 3–15, Table 3–16, and Table 3–33.
Updated Table 3–37, Table 3–38, Table 3–39, and Table 3–40.
Initial release.
MAX V Device Handbook
May 2011 Altera Corporation