|
5M570ZT144C5N Datasheet, PDF (30/30 Pages) Altera Corporation – 3. DC and Switching Characteristics for MAX V Devices | |||
|
◁ |
3â30
Chapter 3: DC and Switching Characteristics for MAX V Devices
Document Revision History
Table 3â41. JTAG Timing Parameters for MAX V Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
tJSXZ
Update register valid output to high impedance
â
25
ns
Notes to Table 3â41:
(1) Minimum clock period specified for 10 pF load on the TDO pin. Larger loads on TDO degrades the maximum TCK frequency.
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and
1.5-V LVCMOS operation, the tJPSU minimum is 6 ns and tJPCO, tJPZX, and tJPXZ are maximum values at 35 ns.
Document Revision History
Table 3â42 lists the revision history for this chapter.
Table 3â42. Document Revision History
Date
May 2011
January 2011
December 2010
Version
1.2
1.1
1.0
Changes
Updated Table 3â2, Table 3â15, Table 3â16, and Table 3â33.
Updated Table 3â37, Table 3â38, Table 3â39, and Table 3â40.
Initial release.
MAX V Device Handbook
May 2011 Altera Corporation
|