EPC8QC100 Datasheet, PDF (27/36 Pages) Altera Corporation – 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet

Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
Table 2–10. Enhanced Configuration Device JTAG Instructions (Part 2 of 2) Note (1)
JTAG Instruction
IDCODE
OPCODE
Description
00 0101 1001 Selects the device IDCODE register and places it between TDI and TDO,
allowing the device IDCODE to be serially shifted out to TDO. The device
IDCODE for all enhanced configuration devices is the same and shown
below:
USERCODE
INIT_CONF
PENDCFG
0100A0DDh
00 0111 1001 Selects the USERCODE register and places it between TDI and TDO,
allowing the USERCODE to be serially shifted out the TDO. The 32-bit
USERCODE is a programmable user-defined pattern.
00 0110 0001 This function initiates the FPGA re-configuration process by pulsing the
nINIT_CONF pin low, which is connected to the FPGA(s) nCONFIG
pin(s). After this instruction is updated, the nINIT_CONF pin is pulsed
low when the JTAG state machine enters Run-Test/Idle state. The
nINIT_CONF pin is then released and nCONFIG is pulled high by the
resistor after the JTAG state machine goes out of Run-Test/Idle
state. The FPGA configuration starts after nCONFIG goes high. As a
result, the FPGA is configured with the new configuration data stored in
flash via ISP. This function can be added to your programming file (POF,
JAM, JBC) in the Quartus II software by enabling the Initiate
configuration after programming option in the Programmer options
window (Options menu).
00 0110 0101 This optional function can be used to hold the nINIT_CONF pin low
during JTAG-based ISP of the enhanced configuration device. This
feature is useful when the external flash interface is controlled by an
external FPGA/processor.
This function prevents contention on the flash pins when both the
controller and external device try to access the flash simultaneously.
Before the enhanced configuration device’s controller can access the
flash memory, the external FPGA/processor needs to tri-state its interface
to flash.This can be ensured by resetting the FPGA using the
nINIT_CONF, which drives the nCONFIG pin and keeps the external
FPGA/processor in the “reset” state. The nINIT_CONF pin is released
when the Initiate Configuration (INIT_CONF) JTAG instruction is issued.
Note to Table 2–10:
(1) Enhanced configuration device instruction register length is 10 and boundary scan length is 174.
f
For more information on the enhanced configuration device JTAG
support, refer to the BSDL files provided at the Altera web site.
Enhanced configuration devices can also be programmed by third-party
flash programmers or on-board processors using the external flash
interface. Programming files (POF) can be converted to an Intel HEX
format file (.hexout) using the Quartus II Convert Programming Files
utility, for use with the programmers or processors.
Altera Corporation
August 2005
2–27
Configuration Handbook, Volume 2