5M160ZM100I5N Datasheet, PDF (27/30 Pages) Altera Corporation – DC and Switching Characteristics for MAX V Devices

Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
3–27
LVDS and RSDS Output Timing Specifications
Table 3–39 lists the emulated LVDS output timing specifications for MAX V devices.
Table 3–39. Emulated LVDS Output Timing Specifications for MAX V Devices
Parameter
Mode
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z/5M1270Z/
5M2210Z
Unit
C4, C5, I5
Min
Max
10
—
304
Mbps
9
—
304
Mbps
8
—
304
Mbps
7
—
304
Mbps
6
Data rate (1), (2)
5
—
304
Mbps
—
304
Mbps
4
—
304
Mbps
3
—
304
Mbps
2
—
304
Mbps
1
—
304
Mbps
t_DUTY
Total jitter (3)
—
45
55
%
—
—
0.2
UI
t_RISE
—
—
450
ps
t_FALL
—
—
450
ps
Notes to Table 3–39:
(1) The performance of the LVDS_E_3R transmitter system is limited by the lower of the two—the maximum data rate supported by LVDS_E_3R
I/O buffer or 2x (F_MAX of the ALTLVDS_TX instance). The actual performance of your LVDS_E_3R transmitter system must be attained through
the Quartus II timing analysis of the complete design.
(2) For the input clock pin to achieve 304 Mbps, use I/O standard with V_CCIO of 2.5 V and above.
(3) This specification is based on external clean clock source.
May 2011 Altera Corporation
MAX V Device Handbook