EPM7064STI44-7 Datasheet, PDF (24/66 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000 Programmable Logic Device Family Data Sheet
Figure 9 shows the timing requirements for the JTAG signals.
Figure 9. MAX 7000 JTAG Waveforms
TMS
TDI
TCK
TDO
Signal
to Be
Captured
Signal
to Be
Driven
t _JCP
t _JCH
t _JCL
t _JPSU
t_JPZX
t_JSSU
t_JPCO
t_JSH
t_JSZX
t_JSCO
t _JPH
t _JPXZ
t_JSXZ
Table 12 shows the JTAG timing parameters and values for MAX 7000S
devices.
Table 12. JTAG Timing Parameters & Values for MAX 7000S Devices
Symbol
Parameter
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPH
t_JPCO
t_JPZX
t_JPXZ
t_JSSU
t_JSH
t_JSCO
t_JSZX
t_JSXZ
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
Min Max Unit
100
ns
50
ns
50
ns
20
ns
45
ns
25 ns
25 ns
25 ns
20
ns
45
ns
25 ns
25 ns
25 ns
f For more information, see Application Note 39 (IEEE 1149.1 (JTAG)
Boundary-Scan Testing in Altera Devices).
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Altera Corporation