EP4CE15E22I7N Datasheet, PDF (24/42 Pages) Altera Corporation – 1. Cyclone IV Device Datasheet

1–24
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–24. Clock Tree Performance for Cyclone IV Devices (Part 2 of 2)
Performance
Device
C6
C7
C8
C8L ⁽¹⁾
C9L ⁽¹⁾
EP4CE55
500
437.5
402
362
265
EP4CE75
500
437.5
402
362
265
EP4CE115
—
437.5
402
362
265
EP4CGX15
500
437.5
402
—
—
EP4CGX22
500
437.5
402
—
—
EP4CGX30
500
437.5
402
—
—
EP4CGX50
500
437.5
402
—
—
EP4CGX75
500
437.5
402
—
—
EP4CGX110 500
437.5
402
—
—
EP4CGX150 500
437.5
402
—
—
Note to Table 1–24:
(1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades.
I7
437.5
437.5
437.5
437.5
437.5
437.5
437.5
437.5
437.5
437.5
I8L ⁽¹⁾
362
362
362
—
—
—
—
—
—
—
Unit
A7
—
MHz
—
MHz
—
MHz
—
MHz
—
MHz
—
MHz
—
MHz
—
MHz
—
MHz
—
MHz
PLL Specifications
Table 1–25 lists the PLL specifications for Cyclone IV devices when operating in the
commercial junction temperature range (0°C to 85°C), the industrial junction
temperature range (–40°C to 100°C), the extended industrial junction temperature
range (–40°C to 125°C), and the automotive junction temperature range (–40°C to
125°C). For more information about the PLL block, refer to “Glossary” on page 1–37.
Table 1–25. PLL Specifications for Cyclone IV Devices ^{(1), (2)} (Part 1 of 2)
Symbol
f_IN ⁽³⁾
f_INPFD
f_VCO ⁽⁴⁾
f_INDUTY
t_{INJITTER_CCJ} ⁽⁵⁾
f_{OUT_EXT} (external clock
output) ⁽³⁾
f_OUT (to global clock)
t_OUTDUTY
t_LOCK
Parameter
Input clock frequency (–6, –7, –8 speed grades)
Input clock frequency (–8L speed grade)
Input clock frequency (–9L speed grade)
PFD input frequency
PLL internal VCO operating range
Input clock duty cycle
Input clock cycle-to-cycle jitter
F_REF  100 MHz
F_REF < 100 MHz
PLL output frequency
Min Typ Max Unit
5
— 472.5 MHz
5
— 362 MHz
5
— 265 MHz
5
— 325 MHz
600 — 1300 MHz
40 — 60
%
— — 0.15
UI
—
— ±750
ps
— — 472.5 MHz
PLL output frequency (–6 speed grade)
—
PLL output frequency (–7 speed grade)
—
PLL output frequency (–8 speed grade)
—
PLL output frequency (–8L speed grade)
—
PLL output frequency (–9L speed grade)
—
Duty cycle for external clock output (when set to 50%) 45
Time required to lock from end of device configuration —
— 472.5 MHz
— 450 MHz
— 402.5 MHz
— 362 MHz
— 265 MHz
50 55
%
—
1
ms
Cyclone IV Device Handbook,
Volume 3
May 2013 Altera Corporation