EP1C20F Datasheet, PDF(23/106 Page) Altera Corporation

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EP1C20F Datasheet, PDF (23/106 Pages) Altera Corporation – Cyclone FPGA Family

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MultiTrack Interconnect

All embedded blocks communicate with the logic array similar to

LAB-to-LAB interfaces. Each block (i.e., M4K memory or PLL) connects

to row and column interconnects and has local interconnect regions

driven by row and column interconnects. These blocks also have direct

link interconnects for fast connections to and from a neighboring LAB.

Table 2â2 shows the Cyclone device's routing scheme.

Table 2â2. Cyclone Device Routing Scheme

Destination

Source

LUT Chain

Local Interconnect

vvvvv

Direct Link

Interconnect

R4 Interconnect

C4 Interconnect

vvvvvvâ â â â â

M4K RAM Block

vvvv

PLL

vvv

Column IOE

Row IOE

vvv

Altera Corporation

May 2008

2â17

Preliminary

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