EPF10K20TC144-4 Datasheet, PDF (2/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Table 2. FLEX 10K Device Features
Feature
Typical gates (logic and
RAM) (1)
Maximum system gates
LEs
LABs
EABs
Total RAM bits
Maximum user I/O pins
EPF10K70
70,000
118,000
3,744
468
9
18,432
358
EPF10K100
EPF10K100A
100,000
158,000
4,992
624
12
24,576
406
EPF10K130V
130,000
211,000
6,656
832
16
32,768
470
EPF10K250A
250,000
310,000
12,160
1,520
20
40,960
470
Note to tables:
(1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum
system gates.
...and More
Features
– Devices are fabricated on advanced processes and operate with
a 3.3-V or 5.0-V supply voltage (see Table 3
– In-circuit reconfigurability (ICR) via external configuration
device, intelligent controller, or JTAG port
– ClockLock^TM and ClockBoost^TM options for reduced clock
delay/skew and clock multiplication
– Built-in low-skew clock distribution trees
– 100% functional testing of all devices; test vectors or scan chains
are not required
Table 3. Supply Voltages for FLEX 10K & FLEX 10KA Devices
5.0-V Devices
EPF10K10
EPF10K20
EPF10K30
EPF10K40
EPF10K50
EPF10K70
EPF10K100
3.3-V Devices
EPF10K10A
EPF10K30A
EPF10K50V
EPF10K100A
EPF10K130V
EPF10K250A
2
Altera Corporation