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EP1K10TC144-2N Datasheet, PDF (2/86 Pages) Altera Corporation – Programmable Logic Device Family | |||
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ACEX 1K Programmable Logic Device Family Data Sheet
...and More
Features
â -1 speed grade devices are compliant with PCI Local Bus
Specification, Revision 2.2 for 5.0-V operation
â Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic.
â Operate with a 2.5-V internal supply voltage
â In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
â ClockLockTM and ClockBoostTM options for reduced clock delay,
clock skew, and clock multiplication
â Built-in, low-skew clock distribution trees
â 100% functional testing of all devices; test vectors or scan chains
are not required
â Pull-up on I/O pins before and during configuration
â Flexible interconnect
â FastTrack® Interconnect continuous routing structure for fast,
predictable interconnect delays
â Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
â Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
â Tri-state emulation that implements internal tri-state buses
â Up to six global clock signals and four global clear signals
â Powerful I/O pins
â Individual tri-state output enable control for each pin
â Open-drain option on each I/O pin
â Programmable output slew-rate control to reduce switching
noise
â Clamp to VCCIO user-selectable on a pin-by-pin basis
â Supports hot-socketing
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Altera Corporation
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