EV1320QI Datasheet, PDF (18/20 Pages) Enpirion, Inc. – The EV1320QI is a DC to DC converter specifically designed for memory termination applications.

Layout Recommendation
Figure 9:Typical Top Side and Bottom Side
Layout Recommendation (Top View)
Figure 9 shows the critical components along with
top and bottom traces of a recommended minimum
footprint EV1320QI layout with ENABLE tied to
VDDQ. Alternate enabling configurations, and the
POK pin would have to be connected and routed
according to the specific customer application.
Please see the Gerber files at
www.altera.com/enpirion for exact dimensions and
the internal layers.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EV1320QI package
as possible. They should be connected to the
device with very short and wide traces. Do not use
thermal reliefs or spokes when connecting the
capacitor pads to the respective nodes. The +V and
GND traces between the capacitors and the
EV1320QI should be as close to each other as
EV1320QI
possible so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: The C1N-C1P capacitors
should be placed as close to the C1N-C1P pins as
possible. Use large copper planes to minimize
resistance and inductance. The C1P and C1N
traces between the capacitors and the EV1320QI
should be as close to each other as possible so
that the gap between the two nodes is minimized,
even under the capacitors.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer (layer 2). This ground plane should be
continuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 4: The VDDQ and VOUT
copper are paralleled on layers 3 and 4 in order to
minimize overall series resistance. Please see
Gerber files.
Recommendation 5: AVIN is the power supply for
the internal control circuits. It should be connected
to the 3.3V bus at a quiet point. A 10µF bypass
capacitor (shown on the backside in Figure 9) is
needed on the AVIN node. If the AVIN supply is
noisy, an optional 1Ω resistor is recommended in
series with AVIN. See Figure 6.
Recommendation 6: The AGND pin does not get
connected to PGND on layer 1. It connects to
PGND on layer 2 ground plane. This provides some
noise isolation between AGND and the noisy
PGND trace on layer 1.
Recommendation 7: The soft-start capacitor CSS
and the AVIN capacitor CAVIN are placed on the
back side in Figure 9 so that the input PGND trace
is not compromised.
Recommendation 8: If POK needs to be used,
place a via to the left of pin 4, and route the POK
trace on layer 3 to the POK resistor. Place the POK
resistor to AVIN such that any modifications to the
traces and placements in this recommended layout
are minimized.
Recommendation 9: Follow all the layout
recommendations as close as possible to optimize
performance. Altera provides schematic and layout
reviews for all customer designs. Please contact
www.altera.com/mysupport for Power Applications
support.
06831
October 11, 2013
www.altera.com/enpirion, Page 18
Rev B