5CEFA7F23I7N Datasheet, PDF (18/58 Pages) Altera Corporation – Cyclone V Device Datasheet

Page 18
Switching Characteristics
Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices—Preliminary (Part 4 of 4)
Symbol/
Description
Conditions
Transceiver
Speed Grade 5 ⁽¹⁾
Transceiver
Speed Grade 6
Transceiver
Speed Grade 7
Unit
Min Typ Max Min Typ Max Min Typ Max
Interface speed
(double-width mode)
—
25 — 163.84 25 — 163.84 25 — 156.25 MHz
Notes to Table 20:
(1) Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices.
(2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(3) The reference clock frequency must be ≥ 307.2 MHz to be fully compliance to CPRI transmit jitter specification at 6.144 Gbps. For more information about
CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(4) The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10^-12.
(5) Altera recommends increasing the V_{CCE_GXBL} and V_{CCL_GXBL} typical value from 1.1 V to 1.2 V for Cyclone V GT FPGA systems which require full compliance
to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone V GT and ST
devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(6) Altera recommends increasing the V_{CCE_GXBL} and V_{CCL_GXBL} typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at
4.9152 Gbps (Cyclone V GT and ST devices) and 6.144 Gbps (Cyclone V GT devices only). For more information about the maximum full duplex channels
recommended in Cyclone V GT devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(7) The maximum supported clock frequency is 100 MHz if the PCIe hard IP block is enabled or 125 MHz if the PCIe hard IP block is not enabled.
(8) Cyclone V GT devices support up to three full duplex channels that is compliant to 6144-Mbps CPRI protocol in every two transceiver banks. For CPRI
6144-Mbps transmit jitter compliance, Altera recommends that you use only up to three full-duplex transceiver channels for two transceiver banks in
CPRI Mode. The transceivers are a grouped in transceiver banks of three channels. For more information about the transceiver bank, refer to the
Transceiver Architecture in Cyclone V Devices chapter.
(9) The device cannot tolerate prolonged operation at this absolute maximum.
(10) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the
Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(11) t_LTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(12) t_LTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
(13) t_{LTD_manual} is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
(14) t_{LTR_LTD_manual} is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR
is functioning in the manual mode.
(15) The rate matcher supports only up to ±300 parts per million (ppm).
(16) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
Cyclone V Device Datasheet
June 2013 Altera Corporation