A8259 Datasheet, PDF (16/24 Pages) Altera Corporation – PROGRAMMABLE INTERRUPT CONTROLLER

a8259 Programmable Interrupt Controller Data Sheet
Figure 6 shows the timing waveforms for the 3-byte interrupt sequence
mode.
Figure 6. 3-Byte Interrupt Sequence Mode Timing Waveforms
X indicates “Don’t Care.”
clk
Level-triggered
interrupt request
or
Edge-triggered
interrupt request
int
ninta
dout[7..0]
X
X
X
X
Call Code
1st Vector
Data
2nd Vector
Data
Level-triggered interrupt
request is clocked by the
falling edge of ninta.
Single-Byte Interrupt Sequence Mode
The single-byte interrupt sequence mode provides an 8-bit interrupt
vector. The interrupt sequence for this mode is as follows:
1. One or more of the ir[7..0] signals are high, which sets the
corresponding bit in the IRR.
2. The a8259 checks the priority and masks for the interrupt, and if
appropriate, sets the int signal.
3. The microprocessor responds by asserting ninta to the a8259.
4. The a8259 latches the ir signal on the falling edge of the ninta
signal (when level-triggered). The a8259 sets the corresponding ISR
bit on the following rising edge of the ninta signal. Simultaneously,
the interrupt request bit is reset, and no data is driven onto the
dout[7..0] bus for this cycle.
5. The microprocessor issues a second ninta pulse. An 8-bit interrupt
vector is driven onto the dout[7..0] bus. See Table 20.
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Altera Corporation