5M240ZM100C5N Datasheet, PDF (16/30 Pages) Altera Corporation – DC and Switching Characteristics for MAX V Devices

3–16
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
1 The default slew rate setting for MAX V devices in the Quartus II design software is
“fast”.
Table 3–24. UFM Block Internal Timing Microparameters for MAX V Devices (Part 1 of 2)
Symbol
Parameter
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z
C4
C5, I5
5M1270Z/ 5M2210Z
C4
C5, I5
Unit
t_ACLK
t_ASU
t_AH
t_ADS
t_ADH
t_DCLK
t_DSS
t_DSH
t_DDS
t_DDH
t_DP
t_PB
t_BP
t_PPMX
Min Max Min Max Min
Address register clock
period
100
—
100
—
100
Address register shift
signal setup to address
20
—
20
—
20
register clock
Address register shift
signal hold to address
20
—
20
—
20
register clock
Address register data in
setup to address register 20
—
20
—
20
clock
Address register data in
hold from address
20
—
20
—
20
register clock
Data register clock period 100
—
100
—
100
Data register shift signal
setup to data register
60
—
60
—
60
clock
Data register shift signal
hold from data register
20
—
20
—
20
clock
Data register data in
setup to data register
clock
20
—
20
—
20
Data register data in hold
from data register clock
20
—
20
—
20
Program signal to data
clock hold time
0
—
0
—
0
Maximum delay between
program rising edge to
UFM busy signal rising
—
960
—
960
—
edge
Minimum delay allowed
from UFM busy signal
going low to program
20
—
20
—
20
signal going low
Maximum length of busy
pulse during a program
—
100
—
100
—
Max Min Max
—
100
— ns
—
20
— ns
—
20
— ns
—
20
— ns
—
20
— ns
—
100
— ns
—
60
— ns
—
20
— ns
—
20
— ns
—
20
— ns
—
0
— ns
960
—
960 ns
—
20
— ns
100
—
100 µs
MAX V Device Handbook
May 2011 Altera Corporation