5SGXMA3H2F35C2N Datasheet, PDF (14/21 Pages) Altera Corporation – Stratix V Device Overview

14
Clocking
SV51001
2014.01.10
The Quartus II software leverages the Stratix V ALM logic structure to deliver the highest performance,
optimal logic usage, and lowest compile times. The Quartus II software simplifies design re-use because it
automatically maps legacy Stratix designs into the new Stratix V ALM architecture.
Clocking
The Stratix V device core clock network is designed to support 717-MHz fabric operations and 1,066-MHz
and 1,600-Mbps external memory interfaces.
The clock network architecture is based on Altera’s proven global, quadrant, and peripheral clock structure,
which is supported by dedicated clock input pins and fractional clock synthesis PLLs. The Quartus II software
identifies all unused sections of the clock network and powers them down, which reduces power consumption.
Fractional PLL
Stratix V devices contain up to 32 fractional PLLs.
You can use the fractional PLLs to reduce both the number of oscillators required on the board and the clock
pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source. In
addition, you can use the fractional PLLs for clock network delay compensation, zero delay buffering, and
transmitter clocking for transceivers. Fractional PLLs can be individually configured for integer mode or
fractional mode with third-order delta-sigma modulation.
Embedded Memory
Stratix V devices contain two types of embedded memory blocks: MLAB (640-bit) and M20K (20-Kbit).
MLAB blocks are ideal for wide and shallow memories. M20K blocks are useful for supporting larger memory
configurations and include ECC.
Both types of memory blocks operate up to 600 MHz and can be configured to be a single- or dual-port
RAM, FIFO, ROM, or shift register. These memory blocks are flexible and support a number of memory
configurations, as shown in the following table.
Table 10: Embedded Memory Block Configuration
MLAB (640 Bits)
32x20
64x10
M20K (20,480 Bits)
512x40
1Kx20
2Kx10
4Kx5
8Kx2
16Kx1
The Quartus II software simplifies design re-use by automatically mapping memory blocks from legacy
Stratix devices into the Stratix V memory architecture.
Altera Corporation
Stratix V Device Overview
Send Feedback