5CGXFC7D6 Datasheet, PDF (14/35 Pages) Altera Corporation – Key Advantages of Cyclone V Devices

14
Package Plan
Resource
PCIe Hard IP Block
FPGA Hard Memory Controller
HPS Hard Memory Controller
ARM Cortex-A9 MPCore Processor
C2
2
1
1
Dual-core
Member Code
C4
C5
2
2⁽⁷⁾
1
1
1
1
Dual-core Dual-core
CV-51001
2013.12.26
C6
2 ⁽⁷⁾
1
1
Dual-core
Related Information
I/O Features in Cyclone V Devices
Provides the number of LVDS channels in each device package.
Package Plan
Table 13: Package Plan for Cyclone V SX Devices
The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O
pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
U672
F896
Member Code
(23 mm)
(31 mm)
FPGA GPIO HPS I/O
XCVR
FPGA GPIO HPS I/O
C2
145
181
6
—
—
C4
145
181
6
—
—
C5
145
181
6
288
181
C6
145
181
6
288
181
XCVR
—
—
9
9
Cyclone V ST
This section provides the available options, maximum resource counts, and package plan for the Cyclone V ST
devices.
The information in this section is correct at the time of publication. For the latest information and to get
more details, refer to the Altera Product Selector.
Related Information
Altera Product Selector
Provides the latest information about Altera products.
Available Options
The following figure shows sample ordering code and lists the options available for Cyclone V ST devices.
(7) _{1 PCIe Hard IP Block in U672 package.}
Altera Corporation
Cyclone V Device Overview
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