EP1K30TC144-3N Datasheet, PDF (11/86 Pages) Altera Corporation – Programmable Logic Device Family

ACEX 1K Programmable Logic Device Family Data Sheet
Figure 3. ACEX 1K EAB in Dual-Port RAM Mode
Clock A
Port A
address_a[]
data_a[]
we_a
clkena_a
Port B
address_b[]
data_b[]
we_b
clkena_b
Clock B
Figure 4. ACEX 1K Device in Single-Port RAM Mode
Dedicated
Clocks
Dedicated Inputs
& Global Signals
Chip-Wide
Reset
Row Interconnect
EAB Local
Interconnect (1)
2
4
8, 4, 2, 1
8, 9, 10, 11
DQ
DQ
DQ
RAM/ROM
256 × 16
Data
In
512
1,024
×
×
8
4
2,048 × 2
Data Out
4, 8, 16, 32
DQ
4, 8
Address
Write Enable
4, 8, 16, 32
13
Column Interconnect
Note:
(1) EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.
Altera Corporation
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