EP1C12Q240C8N Datasheet, PDF (11/106 Pages) Altera Corporation – Section I. Cyclone FPGA Family Data Sheet

Logic Elements
With the LAB-wide addnsub control signal, a single LE can implement a
one-bit adder and subtractor. This saves LE resources and improves
performance for logic functions such as DSP correlators and signed
multipliers that alternate between addition and subtraction depending
on data.
The LAB row clocks [5..0] and LAB local interconnect generate the
LAB-wide control signals. The MultiTrack^TM interconnect's inherent low
skew allows clock and control signal distribution in addition to data.
Figure 2–4 shows the LAB control signal generation circuit.
Figure 2–4. LAB-Wide Control Signals
Dedicated
6
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclkena1
labclkena2
syncload
labclr2
addnsub
labclk1
labclk2
asyncload
or labpre
labclr1
synclr
Logic Elements
The smallest unit of logic in the Cyclone architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a
programmable register and carry chain with carry select capability. A
single LE also supports dynamic single bit addition or subtraction mode
selectable by a LAB-wide control signal. Each LE drives all types of
interconnects: local, row, column, LUT chain, register chain, and direct
link interconnects. See Figure 2–5.
Altera Corporation
May 2008
2–5
Preliminary