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EP3C25F256I7N Datasheet, PDF (10/34 Pages) Altera Corporation – Cyclone III Device Datasheet | |||
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1â10
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
Schmitt Trigger Input
Cyclone III devices support Schmitt trigger input on TDI, TMS, TCK, nSTATUS, nCONFIG,
nCE, CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces hysteresis to the
input signal for improved noise immunity, especially for signal with slow edge rate.
Table 1â12 lists the hysteresis specifications across supported VCCIO range for Schmitt
trigger inputs in Cyclone III devices.
Table 1â12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III Devices
Symbol
Parameter
VSCHMITT
Hysteresis for Schmitt trigger
input
Conditions
VCCIO = 3.3 V
VCCIO = 2.5 V
VCCIO = 1.8 V
VCCIO = 1.5 V
Minimum
200
200
140
110
Typical
â
â
â
â
Maximum Unit
â
mV
â
mV
â
mV
â
mV
I/O Standard Specifications
The following tables list input voltage sensitivities (VIH and VIL), output voltage (VOH
and VOL), and current drive characteristics (IOH and IOL) for various I/O standards
supported by Cyclone III devices. Table 1â13 through Table 1â18 provide the I/O
standard specifications for Cyclone III devices.
Table 1â13. Cyclone III Devices Single-Ended I/O Standard Specifications (1), (2)
I/O Standard
VCCIO (V)
Min Typ Max
VIL (V)
Min Max
VIH (V)
Min
Max
VOL (V)
Max
VOH (V)
Min
IOL
IOH
(mA) (mA)
3.3-V LVTTL (3) 3.135 3.3 3.465 â 0.8
1.7
3.6
0.45
2.4
4
â4
3.3-V LVCMOS (3) 3.135 3.3 3.465 â 0.8
3.0-V LVTTL (3)
2.85 3.0 3.15 â0.3 0.8
3.0-V LVCMOS (3) 2.85 3.0 3.15 â0.3 0.8
2.5-V LVTTL and
LVCMOS (3)
2.375 2.5
2.625 â0.3
0.7
1.7
3.6
0.2
1.7 VCCIO + 0.3 0.45
1.7 VCCIO + 0.3
0.2
1.7
3.6
0.4
VCCIO â 0.2 2
â2
2.4
4
â4
VCCIO â 0.2 0.1 â0.1
2.0
1
â1
1.8-V LVTTL and
LVCMOS
1.71 1.8
1.89
â0.3
0.35 *
VCCIO
0.65 *
VCCIO
2.25
0.45
VCCIO â
0.45
2
â2
1.5-V LVCMOS
1.425 1.5
1.575
â0.3
0.35 *
VCCIO
0.65 *
VCCIO
VCCIO + 0.3
0.25 *
VCCIO
0.75 *
VCCIO
2
â2
1.2-V LVCMOS
1.14
1.2
1.26
â0.3
0.35 *
VCCIO
0.65 *
VCCIO
VCCIO + 0.3
0.25 *
VCCIO
0.75 *
VCCIO
2
â2
3.0-V PCI
2.85
3.0
3.15
â
0.3 *
VCCIO
0.5 *
VCCIO
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO
1.5
â0.5
3.0-V PCI-X
2.85
3.0
3.15
â
0.35*
VCCIO
0.5 *
VCCIO
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO
1.5
â0.5
Notes to Table 1â13:
(1) For voltage referenced receiver input waveform and explanation of terms used in Table 1â13, refer to âSingle-ended Voltage referenced I/O Standardâ
in âGlossaryâ on page 1â27.
(2) AC load CL = 10 pF.
(3) For more detail about interfacing Cyclone III devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III
Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O Systems.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
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