FLEX8000 Datasheet, PDF (1/61 Pages) Altera Corporation – PROGRAMMABLE LOGIC DEVICES FAMILY

®
September 1998, ver. 9.11
FLEX 8000
Programmable Logic
Device Family
Data Sheet
Features...
s Low-cost, high-density, register-rich CMOS programmable logic
device (PLD) family (see Table 1)
– 2,500 to 16,000 usable gates
– 282 to 1,500 registers
s System-level features
– In-circuit reconfigurability (ICR) via external Configuration
EPROM or intelligent controller
– Fully compliant with the peripheral component interconnect
(PCI) standard
– Built-in Joint-Test Action Group (JTAG) boundary-scan test (BST)
circuitry compliant with IEEE Std. 1149.1-1990 on selected devices
– MultiVolt^™ I/O interface enabling device core to run at 5.0 V,
while I/O pins are compatible with 5.0-V and 3.3-V logic levels
– Low power consumption (typical specification less than 0.5 mA
in standby mode)
s Flexible interconnect
– FastTrack^™ Interconnect continuous routing structure for fast,
predictable interconnect delays
– Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
– Dedicated cascade chain that implements high-speed, high-fan-in
logic functions (automatically used by software tools and
megafunctions)
– Tri-state emulation that implements internal tri-state nets
s Powerful I/O pins
– Programmable output slew-rate control reduces switching noise
s Peripheral register for fast setup and clock-to-output delay
Table 1. FLEX 8000 Device Features
Feature
Usable gates
Flipflops
Logic array blocks (LABs)
Logic elements (LEs)
Maximum user I/O pins
JTAG BST circuitry
EPF8282A EPF8452A
EPF8282AV
2,500
4,000
282
452
26
42
208
336
78
120
Yes
No
EPF8636A
6,000
636
63
504
136
Yes
EPF8820A EPF81188A EPF81500A
8,000
820
84
672
152
Yes
12,000
1,188
126
1,008
184
No
16,000
1,500
162
1,296
208
Yes
Altera Corporation
1
A-DS-F8000-09.11