ASM4SSTVF16859 Datasheet, PDF (8/16 Pages) Alliance Semiconductor Corporation – DDR 13-Bit to 26-Bit Registered Buffer

August 2004
rev 2.0
DC Electrical Characteristics - DDRI - 400 (PC3200)
TA = 0°C to 70°C, VDD = 2.6 ± 0.2V, and VDDQ = 2.6 ± 0.2V (unless otherwise stated)
Guaranteed by design. Not 100% production tested.
ASM4SSTVF16859
Symbol Parameters
Test conditions
VIK
II = -18 mA
VOH
IOH = -100 A
IOH = -8 mA
VOL
IOL = 100 A
IOL = 8 mA
II
All inputs VI = VDD or GND
IDD
Standby
RESETB = GND
(static)
Operating VI = VIH(AC) or VIL(AC),
(static) RESETB = VDD
IDDD
Dynamic RESETB = VDD, VI = VIH(AC) or
operating VIL(AC), CLK and CLKB switching _{IO = 0}
(clock only) 50% duty cycle
Dynamic RESETB = VDD, VI = VIH(AC) or
operating (per VIL(AC), CLK and CLKB = switching
each data 50% duty cycle; One data input
input) switching at half clock frequency,
50% duty cycle
rOH
Output high IOH = -16 mA
rOL
Output low IOL = 16 mA
rO(D)
|rOH - rOL| each
IO = 20 mA, TA = 25 C
separate bit
Data inputs V_I = V_REF ± 310 mV, V_ICR = 1.25 V,
Ci
CLK and CLKB VI(PP) = 360 mV
RESETB _{VI = VDD or GND}
VDD
2.5 V
Min Typ
2.5 V to 2.7 V VDD - 0.2
2.5 V
1.95
2.5 V to 2.7 V
2.5 V
2.7 V
2.7 V
2.7 V
2.7 V
30
2.7 V
10
2.5 V to 2.7 V
7
2.5 V to 2.7 V
7
2.6 V
2.6 V
2.5
2.6 V
2.5
2.6V
2.5
Max
-1.2
0.2
0.35
±5
0.01
25
20
20
4
3.5
3.5
3.5
Units
V
V
V
V
V
A
A
mA
A/clock
MHz
/clock
MHz/data
input
W
W
W
pF
pF
pF
DDR 13-Bit to 26-Bit Registered Buffer
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