AS4LC256K16EO Datasheet, PDF (8/25 Pages) Alliance Semiconductor Corporation – 3.3V 256K X 16 CMOS DRAM (EDO)

AS4LC256K16EO
®
Notes
1 I_CC1, I_CC3, I_CC4, and I_CC6 depend on cycle rate.
2 I_CC1 and I_CC4 depend on output loading. Specified values are obtained with the output open.
3 An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
4 AC Characteristics assume t_T = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, V_IL (min) ≥ GND and V_IH (max)
≤ V_CC.
5 V_IH (min) and V_IL (max) are reference levels for measuring timing of input signals. Transition times are measured between V_IH and V_IL.
6 Operation within the t_RCD (max) limit insures that t_RAC (max) can be met. t_RCD (max) is specified as a reference point only. If t_RCD is greater than the
specified t_RCD (max) limit, then access time is controlled exclusively by t_CAC.
7 Operation within the t_RAD (max) limit insures that t_RAC (max) can be met. t_RAD (max) is specified as a reference point only. If t_RAD is greater than the
specified t_RAD (max) limit, then access time is controlled exclusively by t_AA.
8 Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
9 Either t_RCH or t_RRH must be satisfied for a read cycle.
10 t_OFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
11 t_WCS, t_WCH, t_RWD, t_CWD and t_AWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If t_WS ≥ t_WS
(min) and t_WH ≥ t_WH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t_RWD
≥ t_RWD (min), t_CWD ≥ t_CWD (min) and t_AWD ≥ t_AWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell.
If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t_CAA or t_CAC or t_CAP.
14 t_ASC ≥ t_CP to achieve t_PC (min) and t_CAP (max) values.
15 These parameters are sampled and not 100% tested.
Key to switching waveform
Undefined/don’t care
Rising input
Falling input
Read cycle waveform
RAS
t_RCD
t_RAS
t_RC
t_RSH
UCAS,
LCAS
Address
t_CRP
t_ASR
t_RAH
Row Address
t_RAD
t_CSH
t_ASC
t_RCS
t_CAH
t_CAS
t_AR
t_RAL
Col Address
WE
OE
I/O
t_ROH
t_RAC
t_AA
t_CLZ
t_OEA
t_CAC
t_RP
t_RRH
t_RCH
t_OEZ
t_OFF
Data Out
4/11/01; V.1.1
Alliance Semiconductor
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