AS4C64M8D1 Datasheet, PDF (58/64 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

Figure 39. Write without Auto Precharge
CK
CK
CKE
COMMAND
A0-A9
t_CK
t_CH t_CL
t_IS t_IH
t_IS t_IH
NOP
WRITE
t_IS t_IH
Col n
NOP
NOP
t_IH
NOP
NOP
AS4C64M8D1
VALID
PRE
NOP
NOP
ACT
RA
A11,A12
A10
BA0,BA1
Case 1:
t_DQSS=min
DQS
DQ
t_IS t_IH
DIS AP
t_IS t_IH
Bank X
t_DQSS
t_DSH
t_DQSH
t_DSH
t_WPST
t_WPRES
t_WPRE
DI
n
t_DQSL
ALL BANKS
ONE BANKS
t_WR
*Bank X
t_RP
DM
Case 2:
t_DQSS=max
DQS
t_DQSS
t_DSS
t_DQSH
t_WPRES
t_WPRE
t_DQSL
t_DSS
t_WPST
DQ
DI
n
DM
DI n = Data In from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are provided in the programmed order following DI n
DIS AP = Disable Autoprecharge
*=”Don't Care”, if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH
NOP commands are shown for ease of illustration; other commands may be valid at these times
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the +
25% window of the corresponding positive clock edge
Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
RA
RA
BA
Don’t Care
Confidential
57
Rev.2.0 Oct. /2014