AS4C32M16D1A Datasheet, PDF (54/64 Pages) Alliance Semiconductor Corporation – 32M x 16 bit DDR Synchronous DRAM

AS4C32M16D1A-C&I
Figure 34. Auto Refresh Mode
t_{CK tCH tCL}
CK
CK
CKE
t_IS t_IH
VALID
VALID
t_IS t_IH
COMMAND
NOP
PRE
NOP
NOP
AR
NOP
AR
NOP
NOP
ACT
A0-A9
RA
A11,A12
RA
A10
ALL BANKS
ONE BANKS
tIS tIH
RA
BA0,BA1
*Bank(s)
BA
DQS
DQ
DM
tRP
tRFC
tRFC
* = “Don't Care”, if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks)
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH
NOP commands are shown for ease of illustration; other valid commands may be possible after tRFC
DM, DQ and DQS signals are all “Don't Care”/High-Z for operations shown
Don’t Care
49
Rev. 1.0
Mar. /2015