AS4C128M16D2A-25BCN Datasheet, PDF (52/63 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

AS4C128M16D2A-25BCN
AS4C128M16D2A-25BIN
Figure 37. Burst read operation followed by precharge:
(RL=4, AL=0, CL=4, BL=8, t_RTP>2 clocks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
CMD
Post CAS#
READ A
DQS
DQS#
AL = 0
DQ's
NOP
NOP
NOP
AL + 2 + max( t_RTP, 2 t_CK)*
NOP
Precharge A
NOP
NOP
Bank A
Activate
CL = 4
RL= 4
>=t_RAS
>=t_RP
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
A0
A1
A2
A3
A4
A5
A6
A8
>=t_RTP
First 4-bit prefetch Second 4-bit prefetch
*: rounded to next integer.
Figure 38. Burst write operation followed by precharge: WL= (RL-1) =3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
CMD
Post CAS#
Write A
NOP
DQS
DQS#
WL= 3
DQ's
NOP
NOP
NOP
NOP
NOP
Completion of the Burst Write
>=t_WR
NOP
Precharge A
DNA₀ DNA₁ DNA₂ DNA₃
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Rev.1.0 Dec 2015