AS4C64M16D3LA-12BIN Datasheet, PDF (51/85 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

AS4C64M16D3LA-12BIN
AS4C64M16D3LA-12BCN
Table 27. Latencies and timing parameters relevant for Dynamic ODT
Name and
Description
Abbr.
Defined from
Defined to
Definition for all DDR3L
speed pin
Unit
ODT turn-on
Latency
ODTLon
registering external
ODT signal high
turning
termination on
= ODTLon WL-2
tCK
ODT turn-off
Latency
ODTLoff
registering external
ODT signal low
turning
termination off
= ODTLoff WL-2
tCK
ODT Latency for
change RTT
changing from
RTT_Nom to
ODTLcnw
registering external
write command
strength from
RTT_Nom to
OD= TLcnw WL-2
tCK
RTT_WR
RTT_WR
ODT Latency for
change RTT
change from
RTT_WR to
ODTLcwn4
registering external
write command
strength from
RTT_WR to
ODTLc= wn4 4+ODTLoff
tCK
RTT_Nom (BL=4)
RTT_Nom
ODT Latency for
change from
RTT_WR to
RTT_Nom (BL=8)
ODTLcwn8
registering external
write command
change RTT
strength from
RTT_WR to
RTT_Nom
ODTLcwn=8 6+ODTLoff tCK (avg)
Minimum ODT high time
after ODT assertion
ODTH4 registering ODT high
ODT registered
low
= ODTH4 4
tCK (avg)
Minimum ODT
high time
after Write (BL=4)
ODTH4
registering write with
ODT high
ODT registered
low
= ODTH4 4
tCK (avg)
Minimum ODT
high time
after Write (BL=8)
ODTH8
registering write with
ODT high
ODT register low
ODTH8=6
tCK (avg)
RTT change skew
tADC
ODTLcnw
ODTLcwn
RTT valid
tADC(min)=0.3tCK(avg)
tADC(max)=0.7tCK(avg)
tCK (avg)
Note 1: tAOF,nom and tADC,nom are 0.5tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw, and ODTLcwn)
Asynchronous ODT Mode
Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporarily disabled (i.e. frozen)
in precharge power-down (by MR0 bit A12). Based on the power down mode definitions, this is currently Precharge
power down mode if DLL is disabled during precharge power down by MR0 bit A12.
In asynchronous ODT timing mode, internal ODT command is NOT delayed by Additive Latency (AL) relative to the
external ODT command.
In asynchronous ODT mode, the following timing parameters apply: tAONPD min/max, tAOFPD min/max.
Minimum RTT turn-on time (tAONPD min) is the point in time when the device termination circuit leaves high
impedance state and ODT resistance begins to turn on. Maximum RTT turn on time (tAONPD max) is the point in
time when the ODT resistance is fully on.
tAONPDmin and tAONPDmax are measured from ODT being sampled high.
Minimum RTT turn-off time (tAOFPDmin) is the point in time when the devices termination circuit starts to turn off
the ODT resistance. Maximum ODT turn off time (tAOFPDmax) is the point in time when the on-die termination has
reached high impedance. tAOFPDmin and tAOFPDmax are measured from ODT being sample low.
Table 28. ODT timing parameters for Power Down (with DLL frozen) entry and exit
Description
Min
Max
ODT to RTT
turn-on delay
ODT to RTT
turn-off delay
min{ ODTLon * tCK + tAONmin; tAONPDmin } max{ ODTLon * tCK + tAONmax; tAONPDmax }
min{ (WL - 2) * tCK + tAONmin; tAONPDmin } max{ (WL - 2) * tCK + tAONmax; tAONPFmax }
min{ ODTLoff * tCK + tAOFmin; tAOFPDmin } max{ ODTLoff * tCK + tAOFmax; tAOFPDmax }
min{ (WL - 2) * tCK + tAOFmin; tAOFPDmin } max{ (WL - 2) * tCK + tAOFmax; tAOFPDmax }
tANPD
WL - 1
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