AS4C128M16D3LA-12BAN Datasheet, PDF (5/83 Pages) Alliance Semiconductor Corporation – AEC-Q100 Compliant

AS4C128M16D3LA-12BAN
Figure 3. State Diagram
This simplified State Diagram is intended to provide an overview of the possible state transitions and the
commands to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die
termination, and some other events are not captured in full detail.
Power
applied
Power
On
Reset
Procedure
Initialization
MRS,MPR,
Write
Leveling
Self
Refresh
from any
state
RESET
ZQCL
MRS
ZQ
ZQCL,ZQCS
Calibration
Idle
REF Refreshing
ACT
ACT = Active
PRE = Precharge
PREA = Precharge All
MRS = Mode Register Set
REF = Refresh
RESET = Start RESET Procedure
Read = RD, RDS4, RDS8
Read A = RDA, RDAS4, RDAS8
Write = WR, WRS4, WRS8
Write A = WRA, WRAS4, WRAS8
ZQCL = ZQ Calibration Long
ZQCS = ZQ Calibration Short
PDE = Enter Power-down
PDX = Exit Power-down
SRE = Self-Refresh entry
SRX = Self-Refresh exit
MPR = Multi-Purpose Register
Automatic Sequence
Command Sequence
Active
Power
Down
PDX
PDE
WRITE
Writing
WRITE A
Writing
WRITE ^A
Activating
Bank
Activating
WRITE
Precharging
Precharge
Power
Down
READ
READ
READ
READ ^A
Reading
READ A
READ _A
Reading
Confidential
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Rev. 1.0 May 2016