AS4C8M16SA Datasheet, PDF (48/54 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

AS4C8M16SA
Figure 39. Random Row Read (Interleaving Banks)
(Burst Length=4, CAS# Latency=2)
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE ^High
CS#
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
RAS#
CAS#
WE#
BA0,1
A10
RBu
A0-A9, _RBu
A11
DQM
RAu
CBu RAu
CAu
tRP
RBv
RBv
RAv
CBv RAv
tRP
RBw
CAv
tRP
RBw
DQ
Activate
Command
Bank B
Bu0 Bu1 Bu2 Bu3 Au0 Au1 Au2 Au3
Bv0 Bv1 Bv2 Bv3 Av0 Av1 Av2 Av3
Activate
Command
Read Bank A
Bank B
with Auto
Precharge
Read
Bank A
with Auto
Precharge
Activate
Command
Bank B
Activate
Command
Bank A
Read
Bank B
with Auto
Precharge
Read
Bank A
with Auto
Precharge
Activate
Command
Bank B
Don’t Care
Confidential
48
Rev. 2.2
Mar /2014