AS4C16M16SA-6BIN Datasheet, PDF (46/55 Pages) Alliance Semiconductor Corporation – 256M – (16Mx16bit) Synchronous DRAM (SDRAM)

AS4C16M16SA-C&I
Figure 36.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)
CLK
CKE
CS#
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9, _RAx
A11-A12
DQM
DQ
Hi-Z
Activate
Command
Bank A
CAx
RBx
RBx
CBx
RBy
RBy
tRP
Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
Bursting beginning with the starting address
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
Don’t Care
Confidential
45
Rev. 3.0
Mar. /2015