AS4C512M32MD3-15BCN Datasheet, PDF (40/104 Pages) Alliance Semiconductor Corporation – Operating case temperature range

AS4C512M32MD3-15BCN
Bank selection for Precharge by address bits
AB (CA4r) BA2 (CA9r) BA1 (CA8r) BA0 (CA7r)
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
DON’T CARE DON’T CARE DON’T CARE
Precharged Bank(s)
8-bank device
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
Bank 4 only
Bank 5 only
Bank 6 only
Bank 7 only
All Banks
Burst Read followed by precharge
For the earliest possible precharge, the precharge command may be issued BL/2 clock cycles after a Read command. A
new bank active (command) may be issued to the same bank after the Row Precharge time (tRP). A precharge com-
mand can not be issued until after tRAS is satisfied.The minimum READ-to-PRECHARGE time must also satisfy a min-
imum analog time from the rising clock edge that initiates the last 8-bit prefetch of a READ command. tRTP begins BL/2
- 4 clock cycles after the READ command.
T0
T1
CK_t / CK_c
RL
CA0-9
Bank M
Col Addr A Col Addr A
[Cmd]
Read
Nop
t_RTP
DQS_c
DQS_t
DQs
...
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Bank M
Bank M
Row Addr Row Addr
Nop Precharge
Nop
Nop
Activate
Nop
Nop
t_RP
DOUT A₀ DOUT A₁ DOUT A₂ DOUT A₃ DOUT A₄ DOUT A₅ DOUT A₆ DOUT A₇
Burst Write followed by precharge
For write cycles, a delay must be satisfied from the time of the last valid burst input data until the Precharge command
may be issued. This delay is known as the write recovery time (tWR) referenced from the completion of the burst write to
the Precharge command. No Precharge command to the same bank should be issued prior to the tWR delay.
LPDDR3 devices write data to the array in prefetch multiples(prefetch = 8). An internal WRITE operation can only begin
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Rev.1.0 Nov. 2016