AS4C128M8D3 Datasheet, PDF (36/85 Pages) Alliance Semiconductor Corporation – AS4C128M8D3

AS4C128M8D3
 Input Clock frequency change
Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be “stable” during almost all states of
normal operation. This means once the clock frequency has been set and is to be in the “stable state”, the clock
period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking)
specification.
The input clock frequency can be changed from one stable clock rate to another stable clock rate under two
conditions: (1) Self-Refresh mode and (2) Precharge Power-Down mode. Outside of these two modes, it is illegal to
change the clock frequency.
For the first condition, once the DDR3 SDRAM has been successfully placed in to Self-Refresh mode and tCKSRE
has been satisfied, the state of the clock becomes a don’t care. Once a don’t care, changing the clock frequency is
permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh
mode of the sole purpose of changing the clock frequency, the Self-Refresh entry and exit specifications must still be
met. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum
operating frequency specified for the particular speed grade.
The second condition is when the DDR3 SDRAM is in Precharge Power-Down mode (either fast exit mode or slow
exit mode). If the RTT_Nom feature was enabled in the mode register prior to entering Precharge power down mode,
the ODT signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_Nom feature was
disabled in the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The
ODT signal can be registered either LOW or HIGH in this case. A minimum of tCKSRE must occur after CKE goes
LOW before the clock frequency may change. The DDR3 SDRAM input clock frequency is allowed to change only
within the minimum and maximum operating frequency specified for the particular speed grade. During the input
clock frequency change, ODT and CKE must be held at stable LOW levels. Once the input clock frequency is
changed, stable new clocks must be provided to the DRAM tCKSRX before precharge Power Down may be exited;
after Precharge Power Down is exited and tXP has expired, the DLL must be RESET via MRS. Depending on the
new clock frequency additional MRS commands may need to be issued to appropriately set the WR, CL, and CWL
with CKE continuously registered high. During DLL re-lock period, ODT must remain LOW and CKE must remain
HIGH. After the DLL lock time, the DRAM is ready to operate with new clock frequency.
Figure 12. Change Frequency during Precharge Power-down
PREVIOUS CLOCK FREQUENCY
NEW CLOCK FREQUENCY
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Td1
CK#
CK
CKE
tCH tCL
tCK
tIH
tIS
tCKSRE
tCPDED
tCKE
tCHb tCLb
tCKSRX
tCKb
tIH
tIS
tCHb tCLb
tCKb
COMMAND
NOP
NOP
NOP
NOP
NOP
MRS
Te0
Te1
tCHb tCLb
tCKb
NOP
VALID
ADDRESS
ODT
DQS#
DQS
tAOFPD / tAOF
High-Z
DLL
RESET
tXP
VALID
tIH
tIS
DQ
High-z
DM
NOTES
Enter PRECHARGE
Power-Down Mode
Frequency Change
1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down.
Exit PRECHARGE
Power-Down Mode
tDLLK
Indicates a break
in time scale
Don't Care
2. tAOFPD and tAOF must be statisfied and outputs High-Z prior to T1;refer to ODT timing section for exact requirements
3. If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT
signal must continuously be registered LOW ensuring RTT is in an off state, as shown in Figure 13. If the RTT_NOM feature was disabled in the mode
register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case.
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Rev. 3.0
Aug. /2014