AS4C128M16D3LB-12BCN Datasheet, PDF (35/45 Pages) Alliance Semiconductor Corporation – Eight internal banks for concurrent operation

AS4C128M16D3LB-12BCN
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
DDR3L-1600 Speed Bins
Speed Bin
CL-nRCD-nRP
Parameter
Internal read command to first data
Symbol
tAA
Active to read or write delay time
tRCD
Precharge command period
tRP
Active to active/auto-refresh command time
tRC
Active to precharge command period
Average Clock
Cycle Time
CL = 5
CWL = 5
CWL = 6,7
CL = 6
CWL = 5
CWL = 6
CWL = 7
CL = 7
CWL = 5
CWL = 6
CWL = 7
CL = 8
CWL = 5
CWL = 6
CWL = 7
CL = 9 CWL = 5, 6
CWL = 7
CL = 10 CWL = 5, 6
CWL = 7
CWL = 8
CL = 11 CWL = 5, 6,7
CWL = 8
Supported CL setting
Supported CWL setting
tRAS
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
- 12 (DDR3L-1600)
11-11-11
Min
Max
13.75
20
(13.125)
13.75
-
(13.125)
13.75
-
(13.125)
48.75
-
(48.125)
35
9 * tREFI
3.0
3.3
Reserved
Reserved
2.5
3.3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.875
< 2.5
Reserved
Reserved
Reserved
Reserved
1.875
< 2.5
Reserved
Reserved
Reserved
Reserved
1.5
1.875
Reserved
Reserved
1.5
1.875
Reserved
Reserved
Reserved
Reserved
1.25
1.5
5, 6, 7, 8, 9, 10,11
5, 6, 7, 8
Unit
Notes
ns
7
ns
7
ns
7
ns
7
ns
6
ns
1,2,3,5
ns
4
ns
1,2,3,5
ns
4
ns
4
ns
4
ns
1,2,3,5
ns
4
ns
4
ns
1,2,3,5
ns
4
ns
4
ns
1,2,3,5
ns
4
ns
1,2,3,5
ns
4
ns
4
ns
1,2,3
nCK
nCK
Confidential
- 35/45 -
Rev.1.0 Mar 2016