AS4C64M16D2 Datasheet, PDF (34/58 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

AS4C64M16D2
CK#
CK
CMD
ODT
Rtt
t_AOFD
Old setting
EMRS
NOP
NOP
t_{MOD, max}
NOP
NOP
t_IS
t_AOND
NOP
New setting
NOTE 1: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
NOTE 2: "setting" in this diagram is measured from outside.
Figure 10. ODT timing for active standby mode
CK#
CK
CKE
ODT
T0
T1
t_IS
VIH(ac)
Internal
Term Res.
T2
T3
T4
t_AOND
t_IS
VIL(ac)
t_AON,min
t_AON,max
t_AOFD
RTT
T5
T6
t_IS
t_AOF,min
t_AOF,max
Figure 11. ODT timing for power-down mode
Alliance Memory Inc. reserves the right to change products or specification without notice.
33
Rev. 1.1
April. /2012