ASM5P2308A Datasheet, PDF (3/18 Pages) Alliance Semiconductor Corporation – 3.3V Zero-Delay Buffer

September 2005
rev 1.4
Zero Delay and Skew Control
ASM5P2308A
All outputs should be uniformly loaded to achieve Zero Delay between input and output.
1500
1000
500
0
-30 -25 _-20 -15 _{-10 -5}
0
-500
5 ₁₀
15
20
25 30
-1000
-1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
To close the feedback loop of the ASM5P2308A, the FBK pin can be driven from any of the eight available output pins. The
output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this
output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded.
If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback
output and remaining outputs. For zero output-output skew, be sure to load outputs equally.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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