ASM5I9658 Datasheet, PDF (3/14 Pages) Alliance Semiconductor Corporation – 3.3V 1:10 LVCMOS PLL Clock Generator

July 2005
ASM5I9658
rev 0.2
Table 1: Pin Configuration
Pin #
6
7
2
32
3
4
5
28,26,24,
22,20,18,
16,14,12,
10
30
8,9,13,17
21,25,29
Pin Name
PCLK,
PCLK
FB_IN
VCO_SEL
BYPASS
PLL_EN
MR/OE
Q0-9
QFB
GND
1
VCC_PLL
11,15,19,
23,27,31
VCC
I/O
Input
Input
Input
Input
Input
Input
Output
Output
Supply
Supply
Supply
Type
Function
LVPECL LVPECL reference clock signal
LVCMOS PLL feedback signal input, connect to QFB
LVCMOS Operating frequency range select
LVCMOS PLL and output divider bypass select
LVCMOS PLL enable/disable
LVCMOS Output enable/disable (high-impedance tristate) and device reset
LVCMOS Clock outputs
LVCMOS Clock output for PLL feedback, connect to FB_IN
Ground
VCC
VCC
Negative power supply (GND)
PLL positive power supply (analog power supply). It is recommended
to use an external RC filter for the analog power supply pin V_{CC_PLL}.
Please see applications section for details.
Positive power supply for I/O and core. All V_CC pins must be connected
to the positive power supply for correct operation
Table 2: FUNCTION TABLE
Control
PLL_EN
Default
1
0
Test mode with PLL bypassed. The reference
clock (PCLK) is substituted for the internal VCO
output. ASM59658 is fully static and no minimum
frequency limit applies. All PLL related AC
characteristics are not applicable.
1
Selects the VCO output¹
BYPASS
Test mode with PLL and output dividers
bypassed. The reference clock (PCLK) is directly
1
routed to the outputs. ASM59658 is fully static Selects the output dividers.
and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
VCO_SEL
1
VCO ÷ 1 (High frequency range).
f_REF = f_Q0-9 =2. f_VCO
V_CO ÷ 2 (Low frequency range).
f_REF =f_Q0-9 =4.f_VCO
MR/OE
0
Outputs enabled (active)
Outputs disabled (high-impedance state) and
reset of the device. During reset the PLL
feedback loop is open. The VCO is tied to its
lowest frequency. The length of the reset
pulse should be greater than one reference
clock cycle (PCLK).
Note: 1 PLL operation requires BYPASS=1 and PLL_EN=1.
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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