AS4C32M16D1A-CI Datasheet, PDF (27/64 Pages) Alliance Semiconductor Corporation – Internal pipeline architecture

AS4C32M16D1A-C&I
Random Read Accesses Required CAS Latencies (CL=3)
CK
CK
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
Bank,
Col n
Bank,
Col o
Bank,
Col p
Bank,
Col q
DQS
CL=3
DQ
DO
DO DO
DO DO
n
n'
o
o'
p
DO n, etc. =Data Out from column n, etc.
n', etc. =the next Data Out following DO n, etc. according to the programmed burst order
Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted
Reads are to active rows in any banks
Don’t Care
22
Rev. 1.0
Mar. /2015