AS4C256M16D3A-12BAN Datasheet, PDF (27/83 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

AS4C256M16D3A-12BAN
t_RTP
t_WTR
Internal READ Command to
PRECHARGE Command delay
Delay from start of internal write
transaction to internal read command
max
(4nCK,
-
7.5ns)
max
(4nCK,
-
7.5ns)
t_WR
WRITE recovery time
15
-
ns
t_MRD
t_MOD
Mode Register Set command cycle time
Mode Register Set command update delay
4
max
(12nCK,
15ns)
-
t_CK
-
t_CCD
CAS# to CAS# command delay
4
-
t_CK
t_DAL(min) Auto precharge write recovery + prechargetime
WR + tRP
t_CK
t_MPRR
t_RRD
Multi-Purpose Register Recovery Time
ACTIVE to ACTIVE command period
1
max
(4nCK,
7.5ns)
-
t_CK
-
t_FAW
Four activate window
40
-
ns
AC175
45
t_IS(base)
Command and Address setup time to CK,
CK# referenced to Vih(ac) / Vil(ac) levels
AC150
170
AC135
-
-
ps
-
ps
-
ps
t_IH(base)
Command and Address hold time from CK,
CK# referenced to Vih(dc) / Vil(dc) levels
DC100
120
t_IPW
Control and Address Input pulse width for
each input
560
-
ps
-
ps
t_ZQinit
Power-up and RESET calibration time
512
-
t_CK
t_ZQoper
Normal operation Full calibration time
256
-
t_CK
t_ZQCS
t_XPR
t_XS
Normal operation Short calibration time
Exit Reset from CKE HIGH to a valid command
Exit Self Refresh to commands not
requiring a locked DLL
64
max
(5nCK,
t_RFC+
10ns)
max
(5nCK,
t_RFC
+10ns)
-
t_CK
-
-
t_XSDLL
t_CKESR
t_CKSRE
t_CKSRX
Exit Self Refresh to commands requiring a
locked DLL
Minimum CKE low width for Self Refresh
entry to exit timing
Valid Clock Requirement after Self Refresh Entry (SRE)
or Power-Down Entry (PDE)
Valid Clock Requirement before Self Refresh Exit (SRX)
or Power-Down Exit (PDX) or Reset Exit
tDLLK
(min)
tCKE
(min) +
1 nCK
max
(5 nCK,
10ns)
max
(5 nCK,
10ns)
-
t_CK
-
-
-
Exit Power Down with DLL on to any valid command;
max
t_XP
Exit Precharge Power Down with DLL frozen to
commands not requiring a locked DLL
(3 nCK,
-
6ns)
t_XPDLL
Exit Precharge Power Down with DLL
frozen to commands requiring a lockedDLL
max
(10nCK,
-
24ns)
max
t_CKE
CKE minimum pulse width
(3 nCK,
-
5ns)
t_CPDED
t_PD
Command pass disable delay
Power Down Entry to Exit Timing
1
tCKE
(min)
-
t_CK
9*
tREFI
t_ACTPDEN
t_PRPDEN
t_RDPDEN
Timing of ACT command to Power Down entry
Timing of PRE or PREA command to
Power Down entry
Timing of RD/RDA command to Power Down entry
1
1
RL + 4 +
1
-
t_CK
-
t_CK
-
t_CK
Confidential
-2783-
Rev. 1.0 May 2016