AS4C16M16SA Datasheet, PDF (26/54 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

AS4C16M16SA
Figure 24.1. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=2)
CLK
CKE
CS#
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
RAx
A11-A12
DQM
Hi-Z
DQ
Activate
Command
Bank A
CAx
Ax0
Ax1
Ax2
Read
Command
Bank A
Clock Suspend Clock Suspend
1 Cycle
2 Cycles
tHZ
Ax3
Clock Suspend
3 Cycles
Don’t Care
Confidential
26
Rev. 2.0 63nm Mar /2014