4GB-DDR3L-AS4C512M8D3L Datasheet, PDF (26/86 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

4Gb DDR3L - AS4C512M8D3L
Table 18. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 1.35V)
Symbol
Parameter
t_AA
t_RCD
t_RP
t_RC
t_RAS
t_CK(avg)
t_{CK (DLL_OFF)}
t_CH(avg)
t_CL(avg)
t_DQSQ
t_QH
t_LZ(DQ)
t_HZ(DQ)
t_DS(base)
t_DH(base)
t_DIPW
t_RPRE
t_RPST
t_QSH
t_QSL
t_WPRE
t_WPST
t_DQSCK
t_LZ(DQS)
t_HZ(DQS)
t_DQSL
t_DQSH
t_DQSS
t_DSS
t_DSH
t_DLLK
t_RTP
t_WTR
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACTIVE to PRECHARGE command period
CL=5, CWL=5
CL=6, CWL=5
CL=7, CWL=6
Average clock period
CL=8, CWL=6
CL=9, CWL=7
CL=10, CWL=7
CL=11, CWL=8
Minimum Clock Cycle Time (DLL off mode)
Average clock HIGH pulse width
Average Clock LOW pulse width
DQS, DQS# to DQ skew, per group, per access
DQ output hold time from DQS, DQS#
DQ low-impedance time from CK, CK#
DQ high impedance time from CK, CK#
Data setup time to DQS, DQS#
referenced to Vih(ac) / Vil(ac) levels
AC135
Data hold time from DQS, DQS#
referenced to Vih(dc) / Vil(dc) levels
DC90
DQ and DM Input pulse width for each input
DQS,DQS# differential READ Preamble
DQS, DQS# differential READ Postamble
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# differential WRITE Preamble
DQS, DQS# differential WRITE Postamble
DQS, DQS# rising edge output access
time from rising CK, CK#
DQS and DQS# low-impedance time
(Referenced from RL - 1)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
DQS, DQS# differential input low pulse width
DQS, DQS# differential input high pulse width
DQS, DQS# rising edge to CK, CK# rising edge
DQS, DQS# falling edge setup time to
CK, CK# rising edge
DQS, DQS# falling edge hold time from
CK, CK# rising edge
DLL locking time
Internal READ Command to
PRECHARGE Command delay
Delay from start of internal write
transaction to internal read command
-12
Min.
Max.
13.75
20
13.75
-
13.75
-
48.75
-
35
9 * tREFI
3.0
<3.3
2.5
<3.3
1.875
<2.5
1.875
<2.5
1.5
<1.875
1.5
<1.875
1.25
<1.5
8
-
0.47
0.53
0.47
0.53
-
100
0.38
-
-450
225
-
225
25
-
55
360
0.9
0.3
0.4
0.4
0.9
0.3
-225
-450
-
0.45
0.45
-0.27
0.18
0.18
512
max (4nCK,
7.5ns)
max (4nCK,
7.5ns)
-
-
-
-
-
-
-
-
225
225
225
0.55
0.55
0.27
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_CK
t_CK
ps
t_CK
ps
ps
ps
ps
ps
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
ps
ps
ps
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
Confidential
26
Rev. 2.0
Aug. /2014