AS4C1M16S-7TCN Datasheet, PDF (20/54 Pages) Alliance Semiconductor Corporation – 1M x 16 bit Synchronous DRAM (SDRAM)

AS4C1M16S-C&I
Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V±0.3V, TA = -40~85°C) (Note: 5, 6, 7, 8)
Symbol
A.C. Parameter
tRC
Row cycle time
(same bank)
tRCD RAS# to CAS# delay
(same bank)
tRP
Precharge to refresh/row activate
command (same bank)
tRRD Row activate to row activate delay
(different banks)
tRAS Row activate to precharge time
(same bank)
tWR
Write recovery time
tCK
Clock cycle time
CL* = 2
CL* = 3
tCH
Clock high time
tCL
Clock low time
Access time from CLK
tAC
(positive edge)
CL* = 2
CL* = 3
tCCD CAS# to CAS# Delay time
tOH
Data output hold time
tLZ
Data output low impedance
tHZ
Data output high impedance
tIS
Data/Address/Control Input set-up time
tIH
Data/Address/Control Input hold time
tPDE PowerDown Exit set-up time
tREFI Refresh Interval Time
tXSR Exit Self-Refresh to any Command
-6
Min.
Max.
60
-
18
-
18
-
12
-
42
2
7.5
6
2.5
2.5
-
-
1
2
1
-
2
0.8
tIS+tCK
-
tRC+tIS
100K
-
-
-
-
-
6
5.4
-
-
-
5.4
-
-
-
15.6
-
-7
Min.
Max.
63
-
21
-
21
-
14
-
Unit Note
9
9
ns ₉
9
42
2
8
7
2.5
2.5
-
-
1
2
1
-
2
0.8
tIS+tCK
-
tRC+tIS
100K
-
-
-
-
-
6.5
5.4
-
-
-
5.4
-
-
-
15.6
-
tCK
10
ns
11
tCK
10
ns 8
11
11
tCK
s
ns
* CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to VSS. VIH (Max) = 4.6V for pulse width ≤ 3ns.VIL (Min) = -1.0V for pulse
width ≤ 3ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 12.
6. A.C. Test Conditions
Confidential
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Rev. 2.0
March /2015