AS4C32M16MD1A Datasheet, PDF (2/53 Pages) Alliance Semiconductor Corporation – 60 ball FBGA PACKAGE

AS4C32M16MD1A-5BCN
1. GENERAL DESCRIPTION
This AS4C32M16MD1A-5BCN is 536,870,912 bits synchronous double data rate Dynamic RAM. Each 134,217,728 bits bank is
organized as 8,192 rows by 1024 columns by 16 bits fabricated with Alliance Memory’s high performance CMOS technology. This
device uses a double data rate architecture to achieve high- speed operation. The double data rate architecture is essentially a 2n-
prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. Range of operating
frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high
bandwidth and high performance memory system applications.
2. FEATURES
• VDD/VDDQ = 1.7~1.95V
•Data width: x16
•Clock rate: 200MHz
•Partial Array Self-Refresh(PASR)
•Auto Temperature Compensated Self-Refresh(ATCSR)
•Power Down Mode
•Deep Power Down Mode (DPD Mode)
 CAS Latency: 2 and 3
 Burst Length: 2, 4, 8 and 16
 Burst Type: Sequential or Interleave
 64 ms Refresh period
 Interface: LVCMOS
 Operating Temperature Range
Extended (-30°C to +85°C)
•Programmable output buffer driver strength
•Four internal banks for concurrent operation
•Data mask (DM) for write data
•Clock Stop capability during idle periods
•Auto Pre-charge option for each burst access
•Double data rate for data output
•Differential clock inputs (CK and CK )
•Bidirectional, data strobe (DQS)
•PKG Type
x16 : 8.0 x 9.0mm 60 Ball FPBGA (Fine Pitch Ball Grid Array)
Table 1. Speed Grade Information
Speed Grade
Clock Frequency CAS Latency
DDR1-400
200MHz
3
t_RCD (ns)
15
t_RP (ns)
15
Table 2. Ordering Information
Product part No
Org
Temperature
AS4C32M16MD1A-5BCN 32Mx 16 Extended -30°C to +85°C
Max Clock (MHz)
200
Package
60-ball FPBGA
Confidential
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Rev.1.2 July 2016